merging Memory & Logic Solutions Inc.
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
EM680FU16 Series
Low Power, 512Kx16 SRAM
t
WC
Address
t
CW
(2)
CS
1
CS
2
t
A W
t
B W
UB ,LB
t
A S
(3)
WE
t
DW
Data in
Data out
High-Z
Data Valid
t
W R
(4)
t
W P
(1)
t
DH
High-Z
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap(t
WP
) of low CS
1
and low WE. A write begins when CS1 goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS
1
goes high and WE goes high. The t
WP
is
measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS
1
going low to end of write.
3. t
A S
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end or write to the address change. t
WR
applied in case a write ends as CS
1
or WE going high.
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