EM4069
EM4169
EEPROM organization
The EEPROM is organized in 8 words of 16 bits. EEPROM words are counted from 0 to 7. Bits in an EEPROM word are counted
from 0 to 15. When EEPROM readout is initiated (after POR or after return from command to read mode) read out is started from
word 0 and increments to word 7. Readout in a word is started by bit 0 and then increments up to bit 15. After word 7 bit 15 is
read readout continues with word 0 bit 0 without any pause. So it is very important to organize data written in EEPROM in a way
that reader can detect the position of bits in data stream. For Manchester encoding Word 0 and word 4 are factory programmed
and locked (see figure 7a), for BI-phase encoding the 8 words are user free (see figure 7b and 7c). Following tables show how
standard versions are factory programmed.
EEPROM Configuration for Manchester encoding (Version 1 and 11)
Word name
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
Configuration
1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
Fig. 7a
EEPROM Configuration for BI-phase encoding and 64 RF cycles/bit data rate (Version 21)
Word name
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
0
1
2
3
4
5
6
7
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
Configuration
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Fig. 7b
EEPROM Configuration for BI-phase encoding and 32 RF cycles /bit data rate (Version 31)
Word name
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
Configuration
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Fig. 7c
6
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