R
EM4102
Block Diagram
CLOCK
EXTRACTOR
Logic
Clock
COIL1
VDD
AC1
+
Cress
Csup
FULL WAVE
RECTIFIER
AC2
MEMORY
ARRAY
SEQUENCER
-
VSS
COIL2
Serial
Data Out
DATA
MODULATOR
DATA
ENCODER
Modulation
Control
Fig. 5
The EM4102 contains 64 bits divided in five groups of
information. 9 bits are used for the header, 10 row parity
bits (P0-P9), 4 column parity bits (PC0-PC3), 40 data bits
(D00-D93), and 1 stop bit set to logic 0.
Functional Description
General
The EM4102 is supplied by means of an electromagnetic
field induced on the attached coil. The AC voltage is
rectified in order to provide a DC internal supply voltage.
When the last bit is sent, the chip will continue with the
first bit until the power goes off.
1
1
1
1
1
1
1
1
1
9 header bits
8 version bits or
customer ID
D00 D01 D02 D03 P0
D10 D11 D12 D13 P1
D20 D21 D22 D23 P2
D30 D31 D32 D33 P3
D40 D41 D42 D43 P4
D50 D51 D52 D53 P5
D60 D61 D62 D63 P6
D70 D71 D72 D73 P7
D80 D81 D82 D83 P8
Full Wave Rectifier
The AC input induced in the external coil by an incident
magnetic field is rectified by a Graetz bridge. The bridge
will limit the internal DC voltage to avoid malfunction in
strong fields.
32 data bits
Clock Extractor
One of the coil terminals (COIL1) is used to generate the
master clock for the logic function. The output of the clock
extractor drives a sequencer.
D90 D91 D92 D93 P9 10 line parity
PC0 PC1 PC2 PC3 S0 bits
4 column parity bits
Sequencer
The sequencer provides all necessary signals to address
the memory array and to encode the serial data out.
Three mask programmed encoding versions of logic are
available. These three encoding types are Manchester,
biphase and PSK. The bit rate for the first and the second
type can be 64 or 32 periods of the field frequency. For
the PSK version, the bit rate is 16.
The sequencer receives its clock from the COIL1 clock
extractor and generates every internal signal controlling
the memory and the data encoder logic.
The header is composed of the 9 first bits which are all
programmed to "1". Due to the data and parity
organisation, this sequence cannot be reproduced in the
data string. The header is followed by 10 groups of 4 data
bits allowing 100 billion combinations and 1 even row
parity bit. Then, the last group consists of 4 event column
parity bits without row parity bit. S0 is a stop bit which is
written to "0"
Bits D00 to D03 and bits D10 to D13 are customer
specific identification.
These 64 bits are outputted serially in order to control the
modulator. When the 64 bits data string is outputted, the
output sequence is repeated continuously until power
goes off.
Data Modulator
The data modulator is controlled by the signal Modulation
Control in order to induce a high current in the coil. The
coil 2 transistor drives this high current. This will affect the
magnetic field according to the data stored in the memory
array.
Memory Array for Manchester & Bi-Phase encoding
ICs
Copyright © 2005, EM Microelectronic-Marin SA
4
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
