R
EM6152
Functional Description
V
IN
Monitoring
The power-on reset and the power-down reset are
generated as a response to the external voltage level
applied on the V
IN
input. The threshold voltage at which
reset is asserted or released (V
RESET
) is determined by the
external voltage divider between V
DD
and V
SS,
as shown on
Fig. 8. A part of V
DD
is compared to the internal voltage
reference. To determine the values of the divider, the
leakage current at V
IN
must be taken into account as well as
the current consumption of the divider itself. Low resistor
values will need more current, but high resistor values will
make the reset threshold less accurate at high temperature,
due to a possible leakage current at the V
IN
input. The sum
of the two resistors (R
1
+ R
2
) should stay below 500 k
Ω
. The
formula is:
V
RESET
= V
REF
x (1 + R
1
/R
2
).
Example: choosing R
1
= 200 k
Ω
and R
2
= 100 k
Ω
gives
V
RESET
=4.56 V (typical) for version V50 and V53.
At power-up the reset output (
RES
) is held low (see Fig. 5).
When V
IN
becomes greater than V
REF
, the
RES
output is
held low for an additional power-on-reset (POR) delay T
POR
(defined with the external resistor connected at R
OSC
pin).
The T
POR
delay prevents repeated toggling of
RES
even if
V
DD
voltage drops out and recovers. The T
POR
delay allows
the microprocessor’s crystal oscillator time to start and
stabilize and ensures correct recognition of the reset signal
to the microprocessor.
The
RES
output goes active low generating the power-
down reset whenever V
IN
falls below V
REF
. The sensitivity or
reaction time of the internal comparator to the voltage level
on V
IN
is typically 3
μ
s.
Timer Programming
good load regulation a 22
μ
F capacitor (or greater) is
needed on the INPUT (see Fig. 8). Tantalum or aluminium
electrolytic are adequate for the 22
μ
F capacitor; film types
will work but are relatively expensive. Many aluminium
electrolytic have electrolytes that freeze at about –30°C, so
tantalums are recommended for operation below –25°C.
The important parameters of the 22
μ
F capacitor are an
effective series resistance of lower than 3
Ω
and a resonant
frequency above 500 kHz.
A 22
μ
F capacitor (or greater) and a 100 nF capacitor are
required on the OUTPUT to prevent oscillations due to
instability. The specification of the 22
μ
F capacitor is as per
the 22
μ
F capacitor on the INPUT (see previous paragraph).
The EM6152 will remain stable and in regulation with no
external load and the dropout voltage is typically constant as
the input voltage fall below its minimum level (see Table 2).
These features are especially important in CMOS RAM
keep-alive applications.
Power Dissipation
Care must be taken not to exceed the maximum junction
temperature (+125°C). The power dissipation within the
EM6152 is given by the formula:
P
TOTAL
= (V
INPUT
– V
OUTPUT
)
×
I
OUTPUT
+ (V
INPUT
)
×
I
SS
The maximum continuous power dissipation at a given
temperature can be calculated using the formula:
P
MAX
= ( 125°C – T
A
) / R
th(j-a)
where R
th(j-a)
is the thermal resistance from the junction to
the ambient and is specified in Table 2. Note that R
th(j-a)
given in Table 2 assumes that the package is soldered to a
PCB (see figure 16). The above formula for maximum power
dissipation assumes a constant load (i.e. >100 s). The
transient thermal resistance for a single pulse is much lower
than the continuous value.
CAN-Bus Sleep Mode Detector (version 55)
When the microcontroller goes into a standby mode, it
implies that it does not send any pulses on the
TCL
input of
the EM6152. After three reset pulse periods (T
CW
+ T
OW
+
T
WDR
) on the
RES
output, the circuit switches on an internal
resistor of 1 M
Ω
, and it will have a reset pulse of typically 3
ms every 1 second on the
RES
output. When a
TCL
edge
The on-chip oscillator allows the user to adjust the power-on
reset (POR) delay T
POR
and the watchdog time T
WD
by
changing the resistor value of the external resistor R
OSC
connected between the pin R
OSC
and V
SS
(see Fig. 8). The
closed and open window times (T
CW
and T
OW
) as well as the
watchdog reset pulse width (T
WDR
), which are T
TCL
dependent, will vary accordingly. The watchdog time T
WD
can be obtained with figures 9 to 12 or with the Excel
application EM6151ResCalc.xls available on EM website.
T
POR
is equal to T
WD
with the minimum and maximum
tolerances increased by 1% (For Version 53, T
POR
is one
fourth of T
WD
).
Note that the current consumption increases as the
frequency increases.
Voltage Regulator
(rising or falling) appears on the
TCL
input or the power
supply goes down and up, the circuit switches to the R
OSC
.
Watchdog Timeout Period Description
The EM6152 has a 5 V, 400 mA, low dropout voltage
regulator. The low supply current makes the EM6152
particularly suitable for automotive systems which remain
continuously powered. The input voltage range is 2.3 V to
40 V for operation and the input protection includes both
reverse battery (42 V below ground) and load dump
(positive transients up to 45 V). There is no reverse current
flow from the OUTPUT to the INPUT when the INPUT
equals V
SS
. This feature is important for systems which
need to implement (with capacitance) a minimum power
supply hold-up time in the event of power failure. To achieve
Copyright © 2006, EM Microelectronic-Marin SA
rev. B / 06.06
7
The watchdog timeout period is divided into two periods, a
closed window period (T
CW
) and an open window period
(T
OW
), see Fig. 4. If no pulse is applied on the
TCL
input
during the open window period T
OW
, the
RES
output goes
low for a time T
WDR
. When a pulse is applied on the
TCL
input, the cycle is restarted with a close window period.
For example if T
WD
= T
POR
= 100ms, T
CW
= 80 ms, T
OW
=
40ms and T
WDR
= 2.5ms.
When V
IN
recovers after a drop below V
REF
, the pad
RES
is
set low for the time T
POR
during which any
TCL
activation is
disabled.
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