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EM6325CYSP5B-2.9 参数 Datasheet PDF下载

EM6325CYSP5B-2.9图片预览
型号: EM6325CYSP5B-2.9
PDF下载: 下载PDF文件 查看货源
内容描述: 复位电路,带有手动复位 [Reset Circuit with Manual Reset]
分类和应用: 复位电路
文件页数/大小: 8 页 / 230 K
品牌: EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
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EM MICROELECTRONIC
- MARIN SA
Reset Circuit with Manual Reset
Description
The EM6325 is an ultra-low current reset circuit available in a
large variety of configurations and very small packages for
maximum flexibility in all end-applications up to 125°C and
using power supplies between 1.5V and 5.5V.
This circuit monitors the supply voltage of any electronic
system, and generates the appropriate reset signal after a
fixed reset timeout period. The threshold defines the
minimum allowed voltage which guarantees the good
functionality of the system. When V
DD
rises above V
TH
, the
output remains active for an additional delay time. This
allows the system to stabilize before getting fully active.
This circuit features a Manual Reset: an input that asserts
reset when pulled low (
MR
with internal pull-up).
Small SC70-4L, SC70-5L and SOT23-5L packages as well
as ultra-low supply current of 2.9μA make the EM6325 an
ideal choice for portable and battery-operated devices.
EM6325
Features
Manual reset function
200ms reset timeout period (1.6ms, 25ms, 1600ms on
request)
Ultra-low supply current of 2.9μA (V
DD
=3.3V)
Operating temperature range: -40°C to +125°C
±1.5%
reset threshold accuracy
11 reset threshold voltages V
TH
: 4.63V, 4.4V, 3.08V,
2.93V, 2.63V, 2.2V, 1.8V, 1.66V, 1.57V, 1.38V, 1.31V
3 reset output options:
Active-low
RESET
push-pull
Active-low
RESET
open-drain
Active-high
RESET
push-pull
Immune to short negative V
DD
transients
Guaranteed Reset valid down to 0.9V
Threshold hysteresis: 2.1% of V
TH
Very small SOT23-5L, SC70-5L and SC70-4L
Typical Application
V
DD
V
DD
RESET
*
V
DD
RESET
Applications
Computers
Servers and workstations
Modems
Wireless communication
Metering
Playstations
PDA , Webpad
Automotive systems
EM6325
MR
RESET
GND
MPU, DSP
RESET
GND
GND
*
R
EXT
for open-drain version only
Block Diagram
V
DD
Oscillator
Pin Configuration
(top view)
RESET
RESET
push-pull / open-drain
+
Voltage
Reference
-
Reset
Logic
RESET
1
2
3
5
V
DD
GND
RESET
(RESET)
1
2
4
3
V
DD
MR
GND
RESET
push-pull
MR
GND
Filter
4
MR
SOT23-5 / SC70-5
top view
SC70-4
top view
Pin Description
Pin
SOT23-5L / SC70-5L
1
SC70-4L
2
Name
Function
Active-low RESET output. RESET remains low for the reset timeout period and
RESET
2
3
1
2
GND
RESET
then goes high after all reset conditions are deasserted or after
MR goes from low
to high
Ground
Active-high RESET output. RESET remains high for the reset timeout period and
then goes low after all reset conditions are deasserted or after
MR
goes from low to
high
Manual Reset input with an internal pull-up 15k
Ω
resistor. Reset remains active as
long as MR is low and for t
POR
after MR returns high. MR can be driven with a
CMOS output or shorted to ground with a switch
Supply Voltage (5.5V max.)
4
5
3
4
MR
V
DD
Copyright
©
2005, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com