EM6621
6.7 Serial Interface Registers
Table 6.7.1 Register RegSCntl1
Bit
3
2
1
Description
Frequency selection
Frequency selection
Positive or negative clock edge selection for
shift operation
0
MSBnLSB
0
R/W
Shift MSB or LSB value first
Default "0" is: Slave mode external clock, negative edge, LSB first
Name
MS1
MS0
POSnNeg
Reset
0
0
0
R/W
R/W
R/W
R/W
Table 6.7.2 Frequency and Master Slave Mode Selection
MS1
0
0
1
1
MS0
0
1
0
1
Description
Slave mode: Clock from external
Master mode: System clock / 4
Master mode: System clock / 2
Master mode: System clock
Table 6.7.3 Register RegSCntl2
Bit
Name
Reset
R/W
Description
3
Start
0
R/W
Enabling the interface,
2
Status
0
R/W
Ready or Chip Select output on PSP[1]
1
OM[1]
0
R/W
Output mode select 1
0
OM[0]
0
R/W
Output mode select 0
Default "0" is: Interface disabled, status 0, serial mode, output tristate.
Table 6.7.4 Register RegSDataL
Bit
Name
3
SerDataL[3]
2
SerDataL[2]
1
SerDataL[1]
0
SerDataL[0]
Default "0" is: Data equal 0.
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Serial data low nibble
Serial data low nibble
Serial data low nibble
Serial data low nibble
Table 6.7.5 Register RegSDataH
Bit
Name
3
SerDataH[3]
2
SerDataH[2]
1
SerDataH[1]
0
SerDataH[0]
Default "0" is: Data equal 0.
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Serial data high nibble
Serial data high nibble
Serial data high nibble
Serial data high nibble
03/02 REV. D/444
Copyright
2002, EM Microelectronic-Marin SA
25
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
