EM6621
4.1 Oscillation Detection Circuit
At power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry,
and thus the system reset. The CPU of the EM6621 remains in the reset state for the ‘CPU Reset Delay’, to
allow the oscillator to stabilize after power up.
The oscillator is disabled during sleep mode. So when waking up from sleep mode, the CPU of the EM6621
remains in the reset state for the CPU Reset Delay, to allow the oscillator to stabilize. During this time, the
Oscillation Detection Circuit is inhibited.
In active or standby modes, the oscillator detection circuit monitors the oscillator. If it stops for any reason, a
system reset is generated. After clock restart the CPU waits for the CPU Reset Delay before executing the first
instructions.
The oscillation detection circuitry can be inhibited with bit
NoOscWD
= 1 in register
RegVldCntl.
At power up,
and after any system reset, the function is activated.
The ‘CPU Reset Delay’ is 32768 system clocks ( Ck[16] ) long.
4.2 Reset Terminal
During active or standby modes the Reset terminal has a debouncer to reject noise. Reset must therefore be
active for at least 16 ms (system clock = 32 KHz).
When canceling sleep mode, the debouncer is not active (no clock), however, reset passes through an
analogue filter with a time constant of typical. 5µs. In this case Reset pin must be high for at least 10 µs to
generate a system reset.
4.3 Input Port A Reset Function
By writing the
OptInpRSel1
and
OptInpRSel2
registers it is possible to choose any combination of port A input
values to execute a system reset. The reset condition must be valid for at least 16ms (system clock = 32kHz) in
active and standby mode.
OPTInpRSleep
selects the input port A reset function in sleep mode. If set to "1" the occurrence of the selected
combination for input port A reset will immediately trigger a system reset (no debouncer) .
Reset combination selection (InpReset) is done with registers
OptInpRSel1
and
OptInpRSel2.
Following formula is applicable :
InpResPA
=
InpResPA[0]
•
InpResPA[1]
•
InpResPA[2]
•
InpResPA[3]
Figure 7. Input Port A Reset Structure
InpRes1PA[n]
0
0
1
1
n = 0 to 3
InpRes2PA[n]
0
1
0
1
InpResPA[n]
V
SS
PA[n]
not PA[n]
V
DD
BIT
[0]
BIT
[1]
BIT
[2]
Input Port A Reset
Bit[0] Selection
Input Port A Reset
Bit[1] Selection
Input Port A Reset
Bit[2] Selection
InpResPA
i.e. ; - no reset if InpResPA[n] = V
SS
.
- Don't care function on a single bit with
its InpResPA[n] = V
DD
.
- Always Reset if InpResPA[3:0] = 'b1111
BIT
InpRes1PA[3]
[3]
InpRes2PA[3]
Input Port A Reset
Bit[3] Selection
Input
Reset
from
Port A
InpResPA[3]
V
SS
PA[3]
PA[3]
V
DD
0
1 MUX
2
3 1 0
03/02 REV. D/444
Copyright
2002, EM Microelectronic-Marin SA
9
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
