R
V3022
Timing Characteristics (standard temperature range)
V
DD
= 5.0 ±10%, V
SS
= 0V and T
A
=-40 to +85°C
Parameter
Symbol Test Conditions
Min.
Typ.
Max.
Unit
Chip select duration, write cycle
Write pulse duration
Time between two transfers
RAM access time (note 1)
Data valid to Hi-impedance (note 2)
Write data settle time (note 3)
Data hold time (note 4)
Advance write time
PF
response delay
t
CS
t
WR
t
W
t
ACC
t
DF
t
DW
t
DH
t
ADW
t
PF
t
R
t
F
tA
tA
/Ds
/Dt
50
50
100
C
LOAD
= 50pF
10
50
10
10
100
200
200
5
10
50
30
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4
Rise time (all timing waveform
signals)
Fall time (all timing waveform
signals)
CS
delay after
A
/D (note 5)
CS
delay to
A
/D
Note 1
: t
ACC
starts from
RD
, (
DS
) or
CS
, whichever activates last
Typically, t
ACC
= 5 + 0.9 C
EXT
in ns; where C
EXT
(external parasitic capacitance) is in pF
Note 2
: t
DF
starts from
RD
(
DS
) or
CS
, whichever deactivates first
Note 3
: t
DW
ends at
WR
(R/
W
) or
CS
, whichever deactivates first
Note 4
: t
DH
starts from
WR
(R/
W
) or
CS
, whichever deactivates first
Note 5
:
A
/D must come before a
CS
and
RD
or a
CS
and
WR
combination. The user has to guarantee this.
Timing Waveforms
Read Timing for Intel (
RD
and
WR
Pulse) and Motorola (
DS
or
RD
pin tied to
CS
and R/
W
)
Fig. 6a
Copyright © 2004, EM Microelectronic-Marin SA
4
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