V6155
Timer Clearing and RES Action
The watchdog circuit monitors the activity of the
processor. If the user’s software does not send a pulse
to the TCL input within the programmed open window
timeout period, a short watchdog RES pulse is
generated which is equal to T
WD
/40 = 2.5 ms typically
(see Fig. 7).
With the open window constraint, new security is added
to conventional watchdogs by monitoring both software
cycle time and execution. Should software clear the
watchdog too quickly (incorrect cycle time) or too slowly
(incorrect execution) it will cause the system to be reset.
If the software is stuck in a loop which includes the
routine to clear the watchdog, then a conventional
watchdog will not reset even though the software is
malfunctioning; the V6155 will generate a system reset
because the watchdog is cleared too quickly.
If no TCL pulse is applied before the closed and open
windows expire, RES will start to generate square waves
of period (T
CW
+ T
OW
+ T
WDR
). The watchdog will remain
in this state until the next TCL falling edge appears
during an open window, or until a fresh power-up
sequence. The system enable output, EN, can be used
to prevent critical control functions being activated in the
event of the system going into this failure mode (see
section “Enable
-
EN Output”).
The RES output must be pulled up to V
DD
even if the
output is not used by the system (see Fig. 10).
after each closed and open window period. A TCL pulse
coming during the open window clears the watchdog
timer. When the TCL pulse occurs too early (during the
closed window), RES goes active and a new timeout
sequence starts. A voltage drop below the V
REF
level for
longer than typically 5
ms,
overrides the timer and
immediately forces RES active and EN inactive. Any
further TCL pulse has no effect until the next power-up
sequence has completed.
The system enable output, EN, is inactive always when
RES is active and remains inactive after a RES pulse
until the watchdog is serviced correctly 3 consecutive
times (i.e. the TCL pulse must come in the open
window). After three consecutive services of the
watchdog with TCL during the open window, the EN
goes active low.
A malfunctioning system would be repeatedly reset by
the watchdog. In a conventional system critical motor
controls could be energized each time reset goes
inactive (time allowed for the system to restart) and in
this way the electrical motors driven by the system could
function out of control. The V6155 prevents the above
failure mode by using the EN output to disable the motor
controls until software has successfully cleared the
watchdog three times (i.e. the system has correctly
restarted after a reset condition).
Enable
-
EN Output
Combined Voltage and Timer Action
The combination of voltage and timer actions is
illustrated by the sequence of events shown in Fig. 8. On
power-up, when the voltage at V
IN
reaches V
REF
, the
power-on reset, POR, delay is initialized and holds RES
active for the time of the POR delay. A TCL pulse will
have no effect until this power-on reset delay is
completed. After the POR delay has elapsed, RES goes
inactive and the watchdog timer starts acting. If no TCL
pulse occurs, RES goes active low for a short time T
WDR
CAN-Bus Sleep Mode Detector
If the microcontroller is in standby mode that means it
does not have any pulses on the TCL input. After 3 reset
pulse periods (T
CW
+ T
OW
+T
WDR
) on the RES output, the
V6155 switches on an internal resistor of 1 MΩ, and it
will have a reset pulse of typically 3 ms every 1 second
on the RES output. When a TCL edge (rising or falling)
appears on the TCL input or the power supply goes
down and up, the V6155 switches to the R input.
Typical Application
V
DD
V6155
Supply voltage
100 nF
R1
100 kΩ
Address
Decoder
100 kΩ
R
V
IN
TCL
µP
RES
R2
Motor
EN Controls
V
SS
RES
EN
GND
Fig. 10
7
EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
