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EN5322QI 参数 Datasheet PDF下载

EN5322QI图片预览
型号: EN5322QI
PDF下载: 下载PDF文件 查看货源
内容描述: 2电压模式同步降压PWM DC -DC转换器集成电感器 [2 A Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor]
分类和应用: 转换器电感器开关LTE
文件页数/大小: 16 页 / 324 K
品牌: ENPIRION [ ENPIRION, INC. ]
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EN5322QI
Pin Configuration
Figure 2. Pin Diagram, Top View.
Pin Description
PIN
1, 21-24
NAME
NC(SW)
FUNCTION
No Connect. These pins are internally connected to the common drain output of the internal
MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or
voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result
in part malfunction or damage.
Input/Output Power Ground. Connect these pins to the ground electrode of the input and
output filter capacitors. Refer to Layout Considerations section for details.
Voltage and Power Output. Connect these pins to output capacitor(s).
Output Voltage Select. These pins set one of seven preset output voltages and the external
divider option (refer to Electrical Characteristics table for more details), and can be directly
pulled up to V
IN
or pulled down to GND; these pins must not be left floating.
Sense Pin for Internally Programmed Output Voltages with VID Codes. For either VID code or
external resistor divider applications, connect this pin to the last local output filter capacitor for
internal compensation.
Feedback Pin for External Voltage Divider Network. Connect a resistor divider to this pin to set
the output voltage. Use 340 kΩ, 1% or better for the upper resistor.
Analog Ground for the Controller Circuits
Analog Voltage Input for the Controller Circuits. Connect this pin to the input power supply.
Use a 1
μF
bypass capacitor on this pin.
Power OK with an Open Drain Output. Refer to Power OK section.
Input Enable. A logic high signal on this pin enables the output and initiates a soft start. A
logic low signal disables the output and discharges the output to GND. This pin must not be
left floating.
Input Power Supply. Connect to input supply. Decouple with input capacitor(s) to PGND.
2-3, 8-9
4-7
10-12
PGND
VOUT
VS2-0
13
14
15
16
17
18
19-20
VSENSE
VFB
AGND
AVIN
POK
ENABLE
PVIN
©Enpirion
2008 all rights reserved, E&OE
03454
4
4/24/2009
www.enpirion.com
Rev:A