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EN25B80-75HCP 参数 Datasheet PDF下载

EN25B80-75HCP图片预览
型号: EN25B80-75HCP
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位串行闪存与引导和参数部门 [8 Mbit Serial Flash Memory with Boot and Parameter Sectors]
分类和应用: 闪存存储
文件页数/大小: 33 页 / 447 K
品牌: EON [ EON SILICON SOLUTION INC. ]
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EN25B80
Table 3b. Protected Area Sizes- Top Boot Sector Organization
Status Register
Content
BP2
BP1
BP0
Bit
Bit
Bit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Memory Content
Protect Sectors
None
Sector 19
Sector 18 to 19
Sector 17 to 19
Sector 16 to 19
Sector 15 to 19
Sector 8 to 19
All
Addresses
None
0FF000h-0FFFFFh
0FE000h-0FFFFFh
0FC000h-0FFFFFh
0F8000h-0FFFFFh
0F0000h-0FFFFFh
080000h-0FFFFFh
000000h-0FFFFFh
Density(KB)
Portion
None
Upper 1/256
Upper 1/128
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/2
All
None
4KB
8KB
16KB
32KB
64KB
512KB
1024KB
Hold Function
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the
clocking sequence. However, taking this signal Low does not terminate any Write Status Register,
Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition
starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK)
being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with
Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after
Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK)
being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and
Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment
of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the
internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD)
High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold
condition.
Figure 4. Hold Condition Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25