欢迎访问ic37.com |
会员登录 免费注册
发布采购

EN25F05-75WIP 参数 Datasheet PDF下载

EN25F05-75WIP图片预览
型号: EN25F05-75WIP
PDF下载: 下载PDF文件 查看货源
内容描述: 512 Kbit的串行闪存与4KB的部门统一 [512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector]
分类和应用: 闪存
文件页数/大小: 32 页 / 1230 K
品牌: EON [ EON SILICON SOLUTION INC. ]
 浏览型号EN25F05-75WIP的Datasheet PDF文件第11页浏览型号EN25F05-75WIP的Datasheet PDF文件第12页浏览型号EN25F05-75WIP的Datasheet PDF文件第13页浏览型号EN25F05-75WIP的Datasheet PDF文件第14页浏览型号EN25F05-75WIP的Datasheet PDF文件第16页浏览型号EN25F05-75WIP的Datasheet PDF文件第17页浏览型号EN25F05-75WIP的Datasheet PDF文件第18页浏览型号EN25F05-75WIP的Datasheet PDF文件第19页  
EN25F05  
Page Program (PP) (02h)  
The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be  
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write  
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).  
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the in-  
struction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least  
significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the  
current page are programmed from the start address of the same page (from the address whose 8 least  
significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration of the  
sequence.  
The instruction sequence is shown in Figure 11. If more than 256 bytes are sent to the device, pre-  
viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor-  
rectly within the same page. If less than 256 Data bytes are sent to device, they are correctly pro-  
grammed at the requested addresses without having any effects on the other bytes of the same page.  
Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,  
otherwise the Page Program (PP) instruction is not executed.  
As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is t  
)
PP  
is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the  
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page  
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,  
the Write Enable Latch (WEL) bit is reset.  
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1,  
BP0) bits (see Table 3) is not executed.  
Figure 11. Page Program Instruction Sequence Diagram  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc.,  
www.eonssi.com  
15  
Rev. D, Issue Date: 2010/04/15