EN25P16
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Write, Program or Erase instructions.
Status Register.
The Status Register contains a number of status and control bits that can be read or set
(as appropriate) by specific instructions.
BUSY bit.
The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or
Erase cycle.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions.
SRP bit.
The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)
signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in
the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1,
BP0) become read-only bits.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the EN25P16
provides the following data protection mechanisms:
Power-On Reset and an internal timer (t
PUW
) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the
Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction
completion or Bulk Erase (BE) instruction completion or
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register
Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers extra software
protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored
except one particular instruction (the Release from Deep Power-down instruction).
Table 3. Protected Area Sizes Sector Organization
Status Register
Content
BP2
BP1
BP0
Bit
Bit
Bit
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Memory Content
Protect Sectors
All
All
Sector 16 to 31
Sector 24 to 31
Sector 28 to 31
Sector 30 to 31
Sector 31
None
Addresses
000000h-1FFFFFh
000000h-1FFFFFh
100000h-1FFFFFh
180000h-1FFFFFh
1C0000h-1FFFFFh
1E0000h-1FFFFFh
1F0000h-1FFFFFh
None
Density(KB)
2048KB
2048KB
1024KB
512KB
256KB
128KB
64KB
None
Portion
All
All
Upper 1/2
Upper 1/4
Upper 1/8
Upper 1/16
Upper 1/32
None
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
7
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2006/12/25
EON [ EON SILICON SOLUTION INC. ]
