EN25QH256
EN25QH256
256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
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Single power supply operation
- Full voltage range: 2.7-3.6 volt
•
Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
•
256 M-bit Serial Flash
- 256 M-bit/32,768 K-byte/131,072 pages
- 256 bytes per programmable page
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Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#
Dual SPI: CLK, CS#, DQ
0
, DQ
1
, WP#, HOLD#
Quad SPI: CLK, CS#, DQ
0
, DQ
1
, DQ
2
, DQ
3
High performance
80MHz clock rate for Standard SPI
80MHz clock rate for two data bits
50MHz clock rate for four data bits
•
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
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High performance program/erase speed
Page program time: 0.8ms typical
Sector erase time: 50ms typical
Block erase time 400ms typical
Chip erase time: 100 seconds typical
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Lockable 512 byte OTP security sector
•
Support Serial Flash Discoverable
Parameters (SFDP) signature
•
Read Unique ID Number
•
Support High Bank Latch Mode
•
Minimum 100K endurance cycle
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Package Options
- 8 contact VDFN (6x8mm)
- 16 pins SOP 300mil body width
- 24 balls BGA (6x8mm)
- All Pb-free packages are RoHS compliant
•
Industrial temperature Range
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Low power consumption
- 12 mA typical active current
- 1
μA
typical power down current
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Uniform Sector Architecture:
8192 sectors of 4-Kbyte
512 blocks of 64-Kbyte
Any sector or block can be erased individually
GENERAL DESCRIPTION
The EN25QH256 is a 256 Megabit (32,768 K-byte) Serial Flash memory, with enhanced write
protection mechanisms. The EN25QH256 supports the standard Serial Peripheral Interface (SPI), and
a high performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip
Select, Serial DQ
0
(DI), DQ
1
(DO), DQ
2
(WP#) and DQ
3
(HOLD#). SPI clock frequencies of up to 80MHz
are supported allowing equivalent clock rates of 160MHz (80MHz x 2) for Dual Output when using the
Dual Output Fast Read instructions, and SPI clock frequencies of up to 50MHz are supported allowing
equivalent clock rates of 200MHz (50MHz x 4) for Quad Output when using the Quad Output Fast
Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The EN25QH256 is designed to allow either single
Sector/Block
at a time or full chip erase operation.
The EN25QH256 can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector
or block
.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
1
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EON [ EON SILICON SOLUTION INC. ]
