EN29F002A / EN29F002AN
Table 5. EN29F002A Command Definitions
Write
Cycles
Req’d
1
st
2
nd
3
rd
4
th
5
th
6
th
Command
Sequence
Read/Reset
Read/Reset
Read/Reset
AutoSelect
Manufacturer ID
AutoSelect Device ID
(Top Boot)
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
1
4
4
4
4
4
4
6
6
1
1
XXXh F0h
RA
555h AAh AAAh
555h AAh AAAh
555h
555h
555h
555h
555h
555h
xxxh
xxxh
AAh AAAh
AAh AAAh
AAh AAAh
AAh AAAh
AAh AAAh
AAh AAAh
B0h
30h
RD
55h
55h
55h
55h
55h
55h
55h
55h
555h
555h
555h
555h
555h
555h
555h
555h
F0h
90h
90h
90h
90h
A0h
80h
80h
AutoSelect Device ID
(Bottom Boot)
AutoSelect Sector
Protect Verify
Byte Program
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Notes:
RA
000h/
100h
001h/
101h
001h/
101h
SA &
02h
PA
555h
555h
RD
7Fh/
1Ch
7Fh/
92h
7Fh/
97h
00h/
01h
PD
AAh AAAh
AAh AAAh
55h
55h
555h
SA
10h
30h
RA = Read Address: address of the memory location to be read. This one is a read cycle.
RD = Read Data: data read from location RA during Read operation. This one is a read cycle.
PA = Program Address: address of the memory location to be programmed
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the sector to be erased. Address bits A17-A13 uniquely select any sector.
The data is 00h for an unprotected sector and 01h for a protected sector.
Byte Programming Command
Programming the EN29F002A is performed on a byte-by-byte basis using a four bus-cycle operation
(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).
When the program command is executed, no additional CPU controls or timings are necessary. The
program operation is terminated automatically by an internal timer. Address is latched on the falling
edge of
CE
or
W E
, whichever is last; data is latched on the rising edge of
CE
or
W E
, whichever
is first. The program operation is completed when EN29F002A returns the equivalent data to the
programmed location.
Programming status may be checked by sampling data on DQ7 (
DATA
polling) or on DQ6 (toggle
bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is
exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read
mode.
EN29F002A ignores commands written during Byte Programming. If a hardware
RESET
occurs
during Byte Programming, data at the programmed location may get corrupted. Programming is
allowed in any sequence and across any sector boundary.
Chip Erase Command
An auto Chip Erase algorithm is employed when the Chip Erase command sequence is performed.
Although the Chip Erase command requires six bus cycles: two unlock write cycles, a setup
command, two additional unlock write cycles and the chip erase command, the user does not need
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
EON [ EON SILICON SOLUTION INC. ]
