EM47DM0888SBA
Pin Description (Continued)
(Data Strobe)
Output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobe DQS is paired with differential
signal /DQS to provide differential pair signaling to the system during
reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
(Termination Data Strobe)
When enabled via Mode Register A11=1 in
MR1
, DRAM will enable the
same termination resistance function on TDQS/TDQS that is applied to
DQS/DQS. When disabled via mode register A11=0 in
MR1
, DM/TDQS
will provide the data mask function and TDQS is not used.
(Command Inputs)
F3, G3, H3
RAS
,
CAS
,
WE
RAS
,
CAS
and
WE
(along with
CS
) define the command being
entered.
C3,D3
DQS,
DQS
B7,A7
TDQS,
TDQS
(Input Data Mask)
B7
B3,C7,C2,C8,E3,
E8,D2,E7
A2,A9,D7,G2,G8,K
1,K9,M1,M9/A1,A8,
B1,D8,F2,F8,J1,J9,
L1,L9,N1,N9
B9,C1,E2,E9
/B2,B8,C9,D1,D9
H8
DM
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a write
access. DM is sampled on both edges of DQS.
(Data Input/Output)
DQ0~7
Data inputs and outputs are on the same pin.
(Power Supply/Ground)
VDD/VSS
VDDQ
/VSSQ
ZQ
VDD and VSS are power supply for internal circuits.
(DQ Power Supply/DQ Ground)
VDDQ and VSSQ are power supply for the output buffers.
(ZQ Calibration)
Reference pin for ZQ calibration
(Active Low Asynchronous Reset)
N2
Reset is active when
RESET
is LOW, and inactive when
RESET
is
RESET
HIGH. RESET must be HIGH during normal operation. RESET is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD,
i.e. 1.20V for DC high and 0.30V for DC low.
(Reference Voltage)
E1
J8
A3,F1,H1,F9,
H9,J7,N7
VREFDQ
VREFCA
NC
Reference voltage for DQ
(Reference Voltage)
Reference voltage for CA
(No Connection)
No internal electrical connection is present.
Note: Input pins only BA0-BA2, A0-A13,
RAS
,
CAS
,
WE
,
CS
, CKE, ODT and
RESET
do not supply
termination.
May. 2011
6/39
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