eorex
Features
• Fully Synchronous to Positive Clock Edge
• VDD/VDDQ= 1.8V +/- 0.15V Power Supply
• LVCMOS Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms (7.8us)
• Partial Array Self-Refresh (PASR)
• Auto Temperature Compensated
Self-Refresh(TCSR)
by built-in temperature sensor
• Driver strength: normal/weak
EM48BM1684LBA
512Mb (8M
×
4Bank
×
16) Synchronous DRAM
Description
The EM48BM1684LBA is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
8Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 512Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 1.8V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVCMOS.
Available packages:
FBGA 54B 12.5mm x 10mm x 1.2mm.
Ordering Information
Part No
EM48BM1684LBA-75F
Organization
32M X 16
Max. Freq
133MHz @CL3
Package
FBGA -54B
Grade
Commercial
Pb
Free
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
1/19
www.eorex.com
EOREX [ EOREX CORPORATION ]
