eorex
Pin
F2
Name
CLK
Preliminary
EM48AM1644LBB
Pin Description (Simplified)
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
when active All commands are masked when CS is registered
HIGH. CS provides for external bank selection on systems with
multiple memory banks. CS is considered part of the command
code
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A11) is determined by A0 to A11 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA8) is determined by A0 to A8 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
V
DD
and V
SS
are power supply pins for internal circuits.
(Power Supply/Ground)
V
DDQ
and V
SSQ
are power supply pins for the output buffers.
(No Connection)
This pin is recommended to be left No Connection on the
device.
G9,E2
/CS0,/CS1
F3
CKE
H7,H8,J8,J7,J3,
J2,H3,H2,H1,G3,
H9,G2
A0~A11
G7,G8
F8
BA0, BA1
/RAS
F7
/CAS
F9
F1/E8
A8,B9,B8,C9,C8,
D9,D8,E9,E1,D2,
D1,C2,C1,B2,B1,
A2
A9,E7,J9/
A1,E3,J1
A7,B3,C7,D3/
A3,B7,C3,D7
E2
/WE
UDQM/LDQM
DQ0~DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Jul. 2006
3/19
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