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EM481M1644VTC-6FE 参数 Datasheet PDF下载

EM481M1644VTC-6FE图片预览
型号: EM481M1644VTC-6FE
PDF下载: 下载PDF文件 查看货源
内容描述: 64MB ( 1M 】 4Bank 】 16 )同步DRAM [64Mb (1M】4Bank】16) Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 18 页 / 1066 K
品牌: EOREX [ EOREX CORPORATION ]
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eorex
Recommended Power On and Initialization
EM484M1644VTC
The following power on and initialization sequence guarantees the device is preconditioned to each user’s
specific needs. (Like a conventional DRAM) During power on, all V
DD
and V
DDQ
pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed V
DD
+0.3V on any of the input pins or V
DD
supplies. (CLK signal started at same
time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the
precharge command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be
held high during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR)
are also required, and these may be done before or after programming the Mode Register.
Dec. 2007
9/18
www.eorex.com