eorex
Features
• Fully Synchronous to Positive Clock Edge
• Single 3.3V
±0.3V
Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.6us)
EM488M1644VTE
128Mb (2M
×
4Bank
×
16) Synchronous DRAM
Description
The EM488M1644VTE is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 128Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TSOPII 54P 400mil.
Ordering Information
Part No
EM488M1644VTE-7F
EM488M1644VTE-6F
EM488M1644VTE-7FE
EM488M1644VTE-6FE
Organization
8M X 16
8M X 16
8M X 16
8M X 16
Max. Freq
143MHz @CL3
166MHz @CL3
143MHz @CL3
166MHz @CL3
Package
54pin TSOP(ll)
54pin TSOP(ll)
54pin TSOP(ll)
54pin TSOP(ll)
Grade
Commercial
Commercial
Extended
Extended
Pb
Free
Free
Free
Free
* EOREX reserves the right to change products or specification without notice.
Dec. 2007
1/17
www.eorex.com
EOREX [ EOREX CORPORATION ]
