eorex
Preliminary
EM488M3244LBB
Extended Mode Register Set ( EMRS )
The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The
SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. )
The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is
written in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state.
BA1
1
BA0
0
A11
0
A10
0
A9
0
A8
0
A7
0
A6
DS
A5
A4
0
A3
0
A2
A1
PASR
A0
Self Refresh Coverage
All Banks
Two Banks (BA1=0)
One Bank (BA0=BA1=0)
Reserved
Reserved
Half of One Bank (BA0=BA1=0 ,Row Address MSB=0)
Quarter of One Bank (BA0=BA1=0 ,Row Address 2 MSB=0)
Reserved
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Driver Strength
full
1/2 Strength
1/4 Strength
Reserved
A6
0
0
1
1
A5
0
1
0
1
BA1
0
1
MRS
Normal
EMRS
May. 2007
12/19
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