eorex
(V
DD
=3.3V±0.3V, T
A
=0°C ~70° -25° ~ +85°
C,
C
C)
Symbol
t
RC
t
RAS
t
RP
t
RCD
t
RRD
t
CCD
t
DPL
t
BDL
t
ROH
t
REF
Parameter
ACTIVE to ACTIVE Command
(Note 6)
Period
ACTIVE to PRECHARGE
(Note 6)
Command Period
PRECHARGE to ACTIVE
(Note 6)
Command Period
ACTIVE to READ/WRITE Delay
(Note 6)
Time
ACTIVE(one) to ACTIVE(another)
(Note 6)
Command
READ/WRITE Command to
READ/WRITE Command
Date-in to PRECHARGE
Command
Date-in to BURST Stop Command
Data-out to High
CL=3
Impedance from
CL=2
PRECHARGE Command
Refresh Time (4,096 cycle)
-7
Min.
62
42
20
20
14
1
2
1
3
2
64
100k
Max.
EM488M3244VBB
AC Operating Test Characteristics (Continued)
-75
Min. Max.
67
45
20
20
15
1
2
1
3
2
64
100k
Units
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
ms
* All voltages referenced to V
SS
.
Note 6:
These parameters account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole
number)
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each user’s
specific needs. (Like a conventional DRAM) During power on, all V
DD
and V
DDQ
pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed V
DD
+0.3V on any of the input pins or V
DD
supplies. (CLK signal started at same
time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the
precharge command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be
held high during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR)
are also required, and these may be done before or after programming the Mode Register.
Jul. 2006
9/18
www.eorex.com
EOREX [ EOREX CORPORATION ]
