eorex
Features
• Fully Synchronous to Positive Clock Edge
• Single 3.3V
±0.3V
Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 2,048 Refresh Cycles / 32ms (15.625us)
EM481M1622VTC
16Mb (512K
×
2Bank
×
16) Synchronous DRAM
Description
The EM481M1622VTC is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
512K words x 2 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 16Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TSOPII 50P 400mil.
Ordering Information
Part No
EM481M1622VTC-75F
EM481M1622VTC-7F
EM481M1622VTC-6F
EM481M1622VTC-7FE
Organization
1M X 16
1M X 16
1M X 16
1M X 16
Max. Freq
133MHz @CL3
143MHz @CL3
166MHz @CL3
143MHz @CL3
Package
50pin TSOP(ll)
50pin TSOP(ll)
50pin TSOP(ll)
50pin TSOP(ll)
Grade
Commercial
Commercial
Commercial
Extended
-25C~70C
Pb
Free
Free
Free
Free
EM481M1622VTC-6FE
1M X 16
166MHz @CL3
50pin TSOP(ll)
Extended
-25C~70C
Free
Dec. 2007
1/18
www.eorex.com
EOREX [ EOREX CORPORATION ]
