eorex
EM484M1644VTA
Pin Description (Simplified)
Pin
38
Name
CLK
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
19
37
/CS
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
CKE
Row address (A0 to A11) is determined by A0 to A11 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA7) is determined by A0 to A7 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
23~26, 22, 29~35
A0~A11
20, 21
18
BA0, BA1
/RAS
17
/CAS
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
16
/WE
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
39/15
UDQM/LDQM
DQ0~DQ15
VDD/VSS
2, 4, 5, 7, 8, 10,
11, 13, 42, 44, 45,
47, 48, 50, 51, 53
1,14,27/
28,41,54
VDD and VSS are power supply pins for internal circuits.
3, 9, 43, 49/
6, 12, 46, 52
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
VDDQ/VSSQ
(No Connection)
36,40
NC
This pin is recommended to be left No Connection on the
device.
Jun. 2009
www.eorex.com
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EOREX [ EOREX CORPORATION ]
