eorex
TMRC register
Address
01H
Bit7
NAME TMRC
Read or Write
Default Value
W
0
(Preliminary)
EU1010 / EU1011
Bit6
Bit5
WDTEN
R/W
0
Bit4
WDTF
R/W
#
Bit3
TBEN
R/W
0
Bit2
TBF
R/W
#
Bit1
RTCEN
R/W
0
Bit0
RTCF
R/W
#
WDT Divide
W
0
*TMRC.0(RTCF) : real time counter transient flag. Once TRTC signal is transient, this flag will be
set as RTCF=1 by hardware. This bit could be cleared by software.
*TMRC.1(RTCEN) : real time counter enable/disable flag.
RTCEN = 1, enable real time counter;
RTCEN = 0, disable real time counter.
*TMRC.2(TBF) : base timer transient flag. Once TBASE signal is transient, this flag will be set as
TBF=1 by hardware. This bit could be cleared by software.
*TMRC.3(TBEN) : Base timer enable/disable flag.
TBEN = 1, enable base timer;
TBEN = 0, disable base timer.
Watchdog Timer
Watchdog timer block diagram is shown as figure_B. The clock source comes from CPU system clock.
Figure_B
Note:
*Once TMRC.5 (WDTEN) is set as “1”, the watchdog timer will start to count till the watchdog timer
overflows, and then the TMRC.4 (WDTF) is set as “1”. Meanwhile, CPU will have a warm reset by
hardware and the data in addresses $3FFCH and $3FFDH will be loaded into program counter.
Watchdog timer can be cleared by setting TMRC.5 (WDTEN=0).
Please note well that the
EU101x watchdog timer is preset as disable after power on reset. Once watchdog timer is
enabled by setting TMRC.5=1, watchdog timer won’t be stopped by software. Set
TMRC.5=0 will just clear watchdog timer counter.
Aug.2007
8/21
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