eorex
EU1010
WDT divider
TMRC (01H)
bit7
0
bit6
0
FSYS/2
FSYS/4
FSYS/8
FSYS/16
0
1
1
0
1
1
PB ports interrupt
PB6~0, in input mode, could be optioned as external interrupt source by setting PBINT (00H.2) = 1.
When the interrupt enabled and external signal changed from high to low, the PB port interrupt will take
into action and its interrupt vector is $2FF6H and $2FF7H.
A falling edge signal at PB ports will wake up CPU from HALT or STOP mode. When PB port interrupt is
enabled (PBINT=1), CPU will wake up from HALT or STOP mode, and serve PB port interrupt first and
then execute next instruction. If PB port interrupt is disabled, CPU will just be waked up and then
execute next instruction only. User should check which PB port the falling edge signal comes from by
PBF control register. If the falling edge is from PB0, the PBF.0 will be set to “1” by hardware. These flags
could be cleared by software.
Address 02H
NAME PBF
Read or Write
Default Value
Bit7
#
Bit6
PBF6
R/W
0
Bit5
PBF5
R/W
0
Bit4
PBF4
R/W
0
Bit3
PBF3
R/W
0
Bit2
PBF2
R/W
0
Bit1
PBF1
R/W
0
Bit0
PBF0
R/W
0
#
#
Timer0
Timer0 is an 8-bit down count timer. Its clock source comes from CPU main-oscillator (FOSC) or ExCLK,
which is listed in figure 4-3. User can preset timer0 counter by setting data into timer0 preload buffer
T0BF(04H). The data read from T0BF(04H) will be the current count of timer0.
Timer0 will down count by every input clock when T0EN=1. When timer0 down count from 00H to FFH,
T0F will be set to “1” and if T0INT =1, the timer0 interrupt will occur. Timer0 will automatically reload data
from T0BF/04H (timer0 preset buffer). Therefore, user can preset timer0 new data into T0BF(04H)
before timer0 underflow and cause different interrupt time duties. That is, timer0 data will be loaded
from T0BF buffer after T0EN bit is set as “1” or timer0 underflows.
Feb.2009
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EOREX [ EOREX CORPORATION ]
