S1C17M01
Flow meter controller with AFE
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DESCRIPTIONS
The S1C17M01 is an ultra low-power MCU equipped with an MR (magneto resistive) sensor controller that allows an MR
sensor array optimized for flow measurement (recommended sensor: KG1205-61 manufactured by KOHDEN Co., Ltd.) to be
connected directly. This IC includes an LCD driver to display the flow count and the readouts on the indicator, and the
synchronous serial interface, UART, and I2C interface for wireless communication with a remote meter reading system. This
IC allows measurement of various environmental conditions such as a temperature and humidity measurement using the R/F
converter, and a supply voltage measurement using the supply voltage detection circuit.
FEATURES
Model
CPU
CPU core
Other
Embedded Flash memory
Capacity
Erase/program count
Other
Embedded RAM
Capacity
Embedded display RAM
Capacity
Clock generator (CLG)
System clock source
System clock frequency
(Operating frequency)
IOSC oscillator circuit
(boot clock source)
OSC1 oscillator circuit
EXOSC clock input
Other
S1C17M01
Seiko Epson original 16-bit RISC CPU core S1C17
On-chip debugger
32K bytes (for both instructions and data)
50 times (min.) *Programming by the debugging tool ICDmini
Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
4K bytes
32 bytes
3 sources (IOSC/OSC1/EXOSC)
16.3 MHz (max.)
7.37 MHz (typ.) embedded oscillator
5 us (max.) starting time (time from cancelation of SLEEP state to vector table read by the
CPU)
32.768 kHz(typ.) crystal oscillator
Oscillation stop detection circuit included
16.3 MHz (max.) square or sine wave input
Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
19 bits (max.) (Pins are shared with the peripheral I/O.)
8 bits
Generates NMI or watchdog timer reset.
128 – 1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
5 channels
2 channels can generate the SPIA master clock.
20 levels (1.8 to 3.7 V)
Intermittent operation mode
Generates an interrupt or hardware reset according to the detection level evaluation.
1 channel
Baud-rate generator included, IrDA1.0 supported
2 channels
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
1 channel
Baud-rate generator included
32 SEG x 1 to 4 COM (max.), 28 SEG x 5 to 8 COM (max.)
16 levels (2.55 to 3.44 V)
I/O port (PPORT)
Number of general-purpose I/O ports
Number of input interrupt ports
Timers
Watchdog timer (WDT)
Real-time clock (RTCA)
16-bit timer (T16)
Supply voltage detection circuit (SVD)
Detection level
Other
Serial interfaces
UART (UART)
Synchronous Serial Interface (SPIA)
I C (I2C)
LCD driver (LCD8A)
LCD output
LCD contrast
2
EPSON [ EPSON COMPANY ]
