S1C88848
■
PIN LAYOUT DIAGRAM
QFP15-128pin
96
97
65
64
S1C88848
INDEX
128
1
32
33
■
PIN DESCRIPTION
Pin name
V
DD
V
SS
V
D1
V
C1–
V
C5
CA–CG
OSC1
OSC2
OSC3
OSC4
K00–K07
K10/EVIN0
K11/EVIN2
R26/TOUT/REM
R27/TOUT
R34/FOUT
R50/BZ
R51/BZ
P10/SIN
P11/SOUT
P12/SCLK
P13/SRDY
P14–P17
COM0–COM15
COM16–COM31
/SEG66–SEG51
Pin No.
71
72
70
67–63
62–58, 95, 96
73
74
68
69
86–79
78
77
97
98
99
100
101
94
93
92
91
90–87
102–117
56–41
In/out
–
–
–
O
–
I
O
I
O
I
I
I
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
O
Function
Power supply (+) terminal
Power supply (GND) terminal
Internal operating voltage output terminal
LCD drive voltage output terminals
LCD voltage boost/reduce-capacitor connection terminals
OSC1 oscillation input terminal (select crystal or CR oscillation by mask option)
OSC1 oscillation output terminal
OSC3 oscillation input terminal (select crystal, ceramic or CR oscillation by mask option)
OSC3 oscillation output terminal
Input port terminals (K00–K07)
Input port terminal (K10) or event counter external clock input terminal (EVIN0)
Input port terminal (K11) or event counter external clock input terminal (EVIN2)
Output port terminal (R26), programmable timer underflow signal inverted output terminal (TOUT)
or remote-control carrier output terminal (REM) (selectable by mask option)
Output port terminal (R27) or programmable timer underflow signal output terminal (TOUT)
Output port terminal (R34) or clock output terminal (FOUT)
Output port terminal (R50) or buzzer output terminal (BZ)
Output port terminal (R51) or buzzer inverted output terminal (BZ) (selectable by mask option)
I/O port terminal (P10) or serial I/F data input terminal (SIN)
I/O port terminal (P11) or serial I/F data output terminal (SOUT)
I/O port terminal (P12) or serial I/F clock I/O terminal (SCLK)
I/O port terminal (P13) or serial I/F ready signal output terminal (SRDY)
I/O port terminals (P14–P17)
LCD common output terminals
LCD common output terminals or LCD segment output terminals
COM16–COM31 (when 1/32 duty is selected)
SEG66–SEG51 (when 1/16 or 1/8 duty is selected)
COM16, SEG65–SEG51 (when 1/17 duty is selected)
LCD segment output terminals
LCD segment output terminals or DC output terminals (selectable by mask option)
Initial reset input terminal
Test input terminal
SEG0–SEG39
SEG40–SEG50
RESET
TEST
*
1
_______
118–128, 1–29
30–40
76
75
O
O
I
I
∗1
TEST is the terminal used for shipping inspection of the IC. For normal operation be sure it is connected to V
DD
.
3
EPSON [ EPSON COMPANY ]
