Epson Research and Development
Page 15
Vancouver Design Center
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Oscillator
SH-4
BUS
12-bit
TFT
Display
A[25:17]
Decoder
M/R#
CS#
FPDAT15
FPDAT12
D11
D10
CSn#
FPDAT[9:0]
D[9:0]
FPFRAME
FPLINE
FPFRAME
FPLINE
A[16:1]
D[15:0]
WE0#
AB[16:1]
DB[15:0]
WE0#
FPSHIFT
DRDY
FPSHIFT
DRDY
WE1#
BS#
WE1#
S1D13706
BS#
RD/WR#
RD#
GPO
RD/WR#
RD#
RDY#
WAIT#
CKIO
CLKI
RESET#
RESET#
AB0
VSS
Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus)
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Oscillator
SH-3
BUS
A[25:17]
CSn#
M/R#
18-bit
TFT
Display
Decoder
FPDAT[17:0]
FPFRAME
D[17:0]
FPFRAME
CS#
A[16:1]
D[15:0]
AB[16:1]
DB[15:0]
FPLINE
FPSHIFT
DRDY
FPLINE
FPSHIFT
DRDY
WE0#
WE1#
BS#
WE0#
WE1#
S1D13706
BS#
RD/WR#
RD#
GPO
RD/WR#
RD#
WAIT#
WAIT#
CKIO
CLKI
RESET#
RESET#
AB0
VSS
Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus)
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09
EPSON [ EPSON COMPANY ]
