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S1L50992 参数 Datasheet PDF下载

S1L50992图片预览
型号: S1L50992
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度门阵列 [HIGH DENSITY GATE ARRAY]
分类和应用:
文件页数/大小: 12 页 / 96 K
品牌: EPSON [ EPSON COMPANY ]
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DATA SHEET
ASIC
S1L50000
Œ
LINE UP
The
S1L50000
Series comprises 11 types of masters, from which the customer is able to select
the master most suitable.
Total
BC
(Raw Gates)
28710
75774
99198
125772
177062
250160
335858
442112
506688
668552
815468
Master
S1L50282/283/284
S1L50752/753/754
S1L50992/993/994
S1L51252/253/254
S1L51772/773/774
S1L52502/503/504
S1L53352/353/354
S1L54422/423/424
S1L55062/063/064
S1L56682/683/684
S1L58152/153/154
Number
of
Pads
88
144
168
188
224
264
308
352
376
432
480
Number
of
Columns (X)
319
519
594
669
794
944
1094
1256
1344
1544
1706
Number
of
Rows (Y)
90
146
167
188
223
265
307
352
377
433
478
Cell Utilization Ratio (U)
*1
2-layer 3-layer 4-layer
metal
metal
metal
50%
47%
47%
45%
45%
45%
43%
40%
40%
40%
40%
88%
85%
85%
80%
75%
75%
75%
70%
70%
70%
70%
95%
95%
95%
95%
95%
95%
95%
90%
90%
90%
90%
NOTE:
*
1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of
the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only
as an estimate
2
EPSON ELECTRONICS AMERICA, INC.
i
150 River Oaks Pkwy
i
San Jose, CA 95134
i
Tel: (408) 922-0200
i
Fax: (408) 922-0238