DATA SHEET
ASIC
S1L50000
GATE ARRAY DEVELOPMENT FLOW
CUSTOMER
EEA
Product Plan
Functional Spec.
Logical Check
(Simulation)
G/A Development
Request
Schematic Pin
Assignment
NG
Verification
OK
*
Circuit Design
Test Pattern Design
• Test pattern (timing chart)
• Timing wave form
• Marking diagram
• P/O
1
Logical Check
(Simulation)
Timing Check
(Simulation)
2
Delay Analyzing
G/A Development
Refer to Note
NG
NG
EWS
OK
Verification
Verification
OK
*
• Schematic
• Pin assignment
Simulation
File
• Timing wave form
• Marking diagram
• P/O
Place & Route
Delay Analyzing
Post Simulation
Simulation List
NG
Verification
OK
Make Masks
Customer Spec.
(Sign Off)
TS (Test Sample)
Fabrication
NG
Check
OK
ES (Engr. Sample)
Fabrication
NG
OK
ES(TS) Proto.
Approval
MP Setup
ET(TS) Approve
the Prototype
Delivery Spec.
Publication
Delivery Spec.
Approve Delivery
Spec.
Delivery Spec.
Approval
* Jobs are done by customer and EEA engineer. Steps in shadowed boxes are based on customer’s requirement.
NOTE:
When the customer performs all tasks to the point of logical simulations and delay simulations on engineering workstations, etc.,
the route taken is (2, Joint Design). When EEA performs the logical simulations, the route taken is (1, Turnkey Design).
EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
9
EPSON [ EPSON COMPANY ]
