DATA SHEET
ASIC
S1L50000
GATE ARRAY DEVELOPMENT FLOW
CUSTOMER
Product Plan
Functional Spec.
EEA
G/A Development
Request
Schematic Pin
Assignment
•
Test pattern (timing chart)
•
Timing wave form
•
Marking diagram
•
P/O
Logical Check
(Simulation)
1
Circuit Design
Test Pattern Design
Verification
*
OK
NG
Logical Check
(Simulation)
Timing Check
(Simulation)
Delay Analyzing
2
Refer to Note
NG
Verification
EWS
OK
G/A Development
Request
•
Schematic
•
Pin assignment
•
Timing wave form
•
Marking diagram
•
P/O
NG
Verification
*
OK
Simulation
File
Place & Route
Delay Analyzing
Simulation List
NG
Post Simulation
Verification
OK
Customer Spec.
(Sign Off)
Make Masks
TS (Test Sample)
Fabrication
NG
Check
OK
NG
ES (Engr. Sample)
Fabrication
Check
OK
ET(TS) Approve
the Prototype
ES(TS) Proto.
Approval
Delivery Spec.
MP Setup
Delivery Spec.
Publication
Approve Delivery
Spec.
Delivery Spec.
Approval
MP
* Jobs are done by customer and EEA engineer. Steps in shadowed boxes are based on customer’s requirement.
NOTE:
When the customer performs all tasks to the point of logical simulations and delay simulations on engineering workstations, etc.,
the route taken is (2, Joint Design). When EEA performs the logical simulations, the route taken is (1, Turnkey Design).
EPSON ELECTRONICS AMERICA, INC.
i
150 River Oaks Pkwy
i
San Jose, CA 95134
i
Tel: (408) 922-0200
i
Fax: (408) 922-0238
9
EPSON [ EPSON COMPANY ]
