6. Pin Functions
6. Pin Functions
GENERAL (CVDD system)
BGA
-
QFP
29
Name
XRESET
IN
I/O
-
RESET
Reset signal
Clock frequency selection
Set the frequency input from the clock source (CLKIN
or XI pin).
1: 24 MHz 0: 12 MHz
Clock source selection
Set whether the clock source is input from the CLKIN
or XI pin.
1: CLKIN 0: XI
Clock input
12 MHz / 24MHz
If the clock input is from the XI pin, set this pin to Low.
Clock output
Refer to the S1R72U01 Technical Manual for
information on how to change the clock output.
48 MHz / 24 MHz / 12 MHz / 6 MHz / 3 MHz / STOP
Pin description
-
39
CLKSEL
IN
-
-
41
CLK_Source
IN
-
-
40
CLKIN
IN
-
-
42
CLKOUT
OUT
Low
OSC (LVDD system)
BGA
QFP
Name
I/O
RESET
Pin description
Internal oscillator circuit input
If the clock input is from the CLKIN pin, set this pin to
Low.
12 MHz / 24 MHz
Internal oscillator circuit output
If the clock input is from the CLKIN pin, leave this pin
open.
-
10
XI
IN
-
-
11
XO
OUT
-
TEST (LVDD, CVDD systems)
BGA
-
-
QFP
44
37
Name
TSTEN
ATPGEN
I/O
IN(PD)
IN(PD)
-
-
RESET
Pin description
Test pin (*1); not intended for use by user
Test pin (*1); not intended for use by user
PD: Pull-down I/Os are used.
*1
This is pulled down inside the LSI. However, we recommend fixing it at Low on the circuit board.
USB (UVDD3 system)
BGA
QFP
Name
I/O
RESET
Pin description
VBUS input pin
VBUS input pin when S1R72U01 is used as USB
device. Leave this pin open when using S1R72U01
as a USB host.
USB data line
USB data line
Data+
Data-
-
9
VBUS
IN
-
-
-
8
7
DP
DM
BI
BI
Hi-Z
Hi-Z
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
7
EPSON [ EPSON COMPANY ]
