PF841-03
SLA9000F Series
qHigh
speed, high integration gate array.
qNumber
of gates mounted: 2.7K to 44K gates.
s
DESCRIPTION
The SLA9000F series is a SOG type CMOS gate which has realized high speed, high integration and high
driving capability. This series is offered with 2,784 to 44,070 gates to ensure an optimum application for any
mid size high speed systems.
This series is designed to operate on both 5 V and 3 V systems to correspond to increasing low-voltage
oriented applications. Simplified level shifter cell is available on this series. And, the
µA
order low noise output
cell of the series has made it suitable for small size, handy equipments and many other applications.
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FEATURES
q
Super-high density (adopting 1.0µm silicon gate CMOS with 2-metal layer)
q
High-speed operation (operation delay of internal gate = 0.3ns at 5.0V, 2-input Power NAND standard)
q
Simplified level shifter cells available
q
Output drivability (I
OL
= 0.1, 2, 6, 12, 24 mA when 5.0V, I
OL
= 0.1, 1, 3, 6, 12mA when 3.3V)
q
On-chip RAM available
q
Low noise output cells available
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PRODUCT LINEUP
Master
Total BCs (Raw Gates)
Usable Bcs
Number of PADs
Internal Gates
Propagation
Input Buffers
Delay
Output Buffers
I/O Level
Input Mode
Output Mode
SLA902F
2,784
1,809
80
SLA904F
4,392
2,854
100
SLA907F
7,872
4,723
128
SLA909F
9,540
5,724
144
SLA913F
13,144
7,229
160
SLA919F
19,350
10,642
184
SLA927F
27,234
13,617
208
SLA944F
44,070
22,035
256
tpd = 0.30ns (standard at 5.0V), tpd = 0.43ns (standard at 3.3V)
tpd = 0.91ns (standard at 5.0V), tpd = 1.08ns (standard at 3.3V)
tpd = 3.5ns (standard at 5.0V), tpd = 4.2ns (standard at 3.3V) CL = 50pF
TTL, CMOS
TTL, CMOS, Pull-up/Pull-down, Schmitt, 3.0/3.3/5.0V Level interface
Normal, Open drain, 3-state, Bi-directional, 3.0/3.3/5.0V Level interface
1