ESMT
Pin Assignment
AD62550A
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
MSDA
MSCL
PDO
Type
I/O
O
O
O
O
O
I
O
P
O
O
P
P
O
O
P
Description
I
2
C’s SDA of Master mode
I
2
C’s SCL of master mode
Power-down output
(Note1)
Serial audio output
(Note1)
L/R clock output(Fs)
(Note1)
BCLK output(64xFs)
(Note1)
Serial audio data input
Master clock(256xFs)
Ground for right channel
Right channel output-
Right channel output+
Supply for right channel
Supply for left channel
Left channel output+
Left channel output-
Ground for left channel
Characteristics
Schmitt trigger TTL input buffer
SDATAO
LRCIN
BCLK
SDATAI
MCLK
GNDR
RB
RA
VDDR
VDDL
LA
LB
GNDL
Schmitt trigger TTL input buffer
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2007
Revision: 1.3
2/14
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
