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F25L16PA-100DG 参数 Datasheet PDF下载

F25L16PA-100DG图片预览
型号: F25L16PA-100DG
PDF下载: 下载PDF文件 查看货源
内容描述: 3V只有16兆位串行闪存,配有双 [3V Only 16 Mbit Serial Flash Memory with Dual]
分类和应用: 闪存
文件页数/大小: 33 页 / 471 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V
Standard, Dual SPI
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 100MHz
(100MHz / 200MHz equivalent Dual SPI)
Low power consumption
- Active current: 35 mA
- Standby current: 30
μ
A
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Byte programming time: 7
μ
s (typical)
- Page programming time: 1.5 ms (typical)
Erase
- Chip erase time 10 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
Page Programming
- 256 byte per programmable page
F25L16PA
3V Only 16 Mbit Serial Flash Memory with Dual
Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Byte Program operations
Lockable 4K bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L16PA –50PG
F25L16PA –100PG
F25L16PA –50PAG
F25L16PA –100PAG
F25L16PA –50DG
F25L16PA –100DG
Speed
50MHz
Package
8 lead SOIC
150mil
150mil
200mil
200mil
300mil
300mil
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
100MHz 8 lead SOIC
50MHz
8 lead SOIC
100MHz 8 lead SOIC
50MHz
100MHz
8 lead PDIP
8 lead PDIP
GENERAL DESCRIPTION
The F25L16PA is a 16Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 8,192 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction. The device also can be
programmed to decrease total chip programming time with Auto
Address Increment (AAI) programming.
The device features sector erase architecture. The memory array
is divided into 512 uniform sectors with 4K byte each; 32 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.4
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