欢迎访问ic37.com |
会员登录 免费注册
发布采购

F25L32PA-50PHG 参数 Datasheet PDF下载

F25L32PA-50PHG图片预览
型号: F25L32PA-50PHG
PDF下载: 下载PDF文件 查看货源
内容描述: 3V只有32兆位串行闪存,配有双 [3V Only 32 Mbit Serial Flash Memory with Dual]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 36 页 / 373 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号F25L32PA-50PHG的Datasheet PDF文件第2页浏览型号F25L32PA-50PHG的Datasheet PDF文件第3页浏览型号F25L32PA-50PHG的Datasheet PDF文件第4页浏览型号F25L32PA-50PHG的Datasheet PDF文件第5页浏览型号F25L32PA-50PHG的Datasheet PDF文件第6页浏览型号F25L32PA-50PHG的Datasheet PDF文件第7页浏览型号F25L32PA-50PHG的Datasheet PDF文件第8页浏览型号F25L32PA-50PHG的Datasheet PDF文件第9页  
ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V
Standard and Dual SPI
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz / 100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI)
Low power consumption
- Active current: 35 mA
- Standby current: 30
μ
A
- Deep Power Down current: 5
μ
A
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Byte programming time: 7
μ
s (typical)
- Page programming time: 1.5 ms (typical)
Erase
- Chip erase time 25 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
Page Programming
- 256 byte per programmable page
F25L32PA
3V Only 32 Mbit Serial Flash Memory with Dual
Lockable 2K bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L32PA –50PAG
F25L32PA –86PAG
F25L32PA –100PAG
F25L32PA –50PHG
F25L32PA –86PHG
F25L32PA –100PHG
Speed
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
Package
8 lead SOIC
8 lead SOIC
8 lead SOIC
16 lead SOIC
16 lead SOIC
16 lead SOIC
200mil
200mil
200mil
300mil
300mil
300mil
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The F25L32PA is a 32Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard and Dual
Serial Peripheral Interface (SPI). ESMT’s memory devices
reliably store memory data even after 100,000 programming and
erase cycles.
The memory array can be organized into 16,384 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
is divided into 1024 uniform sectors with 4K byte each; 64
uniform blocks with 64K byte each. Sectors can be erased
individually without affecting the data in other sectors. Blocks can
be erased individually without affecting the data in other blocks.
Whole chip erase capabilities provide the flexibility to revise the
data in the device. The device has Sector, Block or Chip Erase
but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0
1/36