ESMT
F49L800UA/F49L800BA
Reset Mode :
valid addresses on the device address inputs produce
valid data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Read Command” section for more information.
Refer to the AC Read Operations table 10 for timing
specifications and to Figure 5 for the timing diagram. ICC1
in the DC Characteristics table represents the active
current specification for reading array data.
Hardware Reset
When the
pin is driven low for at least a
RESET
period of tRP, the device immediately terminates any
operation in progress, tri-states all output pins, and
ignores all read/write commands for the duration of the
pulse. The device also resets the internal state
RESET
machine to reading array data. The operation that was
interrupted should be reinitiated later once the device is
ready to accept another command sequence, to ensure
the data integrity.
Write Mode
To write a command or command sequence (which
includes programming data to the device and erasing
The current is reduced for the duration of the
RESET
is held at VSS±0.3V, the device
pulse. When
RESET
draws CMOS standby current (ICC4). If
sectors of memory), the system must drive
and
CE
WE
to VIH. The “Program Command” section
is held
RESET
to VIL, and
OE
at VIL but not within VSS±0.3V, the standby current will
be greater.
has details on programming data to the device using
standard command sequences.
An erase operation can erase one sector, multiple
sectors, or the entire device. Tables 1 and 2 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to uniquely
select a sector. The “Software Command Definitions”
section has details on erasing a sector or the entire chip,
or suspending/resuming the erase operation.
The
pin may be tied to system reset circuitry.
RESET
A system reset would thus reset the Flash memory,
enabling the system to read the boot-up firm-ware from
the Flash memory.
If
is asserted during a program or erase
RESET
embedded algorithm operation, the RY/
pin remains
BY
When the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Auto-select Mode and Auto-select
Command sections for more information. ICC2 in the DC
Characteristics table represents the active current
specification for the write mode. The “AC Characteristics”
section contains timing specification tables and timing
diagrams for write operations.
a "0" (busy) until the internal reset operation is
complete, which requires a time of tREADY (during
Embedded Algorithms). The system can thus monitor
RY/
to determine whether the reset operation is
BY
complete.
If
is asserted when a program or erase
RESET
operation is not executing , i.e. the RY/
is “1”, the
BY
reset operation is completed within a time of tREADY (not
during Embedded Algorithms). The system can read
data after tRH when the
Refer to the AC Characteristics tables 13 for Hardware
Reset section & Figure 23 for the timing diagram.
pin returns to VIH.
RESET
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain unchanged for over
250ns. The automatic sleep mode is independent of the
Read Mode
,
, and
control signals. Standard address
OE
WE
CE
To read array data from the outputs, the system must
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and
always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
drive the
and
pins to VIL.
is the power
CE
OE
CE
control and selects the device.
is the output
OE
control and gates array data to the output pins.
WE
should remain at VIH. The internal state machine is set
for reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious
alteration of the memory content occurs during the
power transition.
Word / Byte Mode
This pin control the I/O configuration of device. When
BYTE = VIH or Vcc ± 0.3V. The I/O configuration is x16
and the pin of D15/A-1 is bi-direction Data I/O. However,
No command is necessary in this mode to obtain array
data. Standard microprocessor’s read cycles that assert
BYTE = VIL or VSS ± 0.3V. The I/O configuration would
be x8 and The pin of DQ15/A-1 only address input pin.
You must define the function of this pin before enable this
device.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision: 1.2
7/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
