ESMT
SDRAM
M12L128168A
2M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
ORDERING INFORMATION
PRODUCT NO.
M12L128168A-5TG
M12L128168A-5BG
M12L128168A-6TG
M12L128168A-6BG
M12L128168A-7TG
M12L128168A-7BG
MAX FREQ. PACKAGE
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
54 TSOP II
54 Ball FBGA
54 TSOP II
54 Ball FBGA
54 TSOP II
54 Ball FBGA
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Pin Arrangement
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
1/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
