ESMT
Mode Register
11
0
11
x
11
11
x
11
0
10
0
10
x
10
10
x
10
0
9
0
9
1
9
9
x
9
0
8
0
8
0
8
1
8
1
8
0
7
1
7
0
7
0
7
1
7
0
6
5
4
4
4
3
3
WT
3
3
v
3
WT
2
2
BL
2
2
v
2
1
1
v
1
BL
0
Use in future
6
v
6
5
4
v
v
5
4
LTMODE
0
v
0
Vender Specific
Mode Register Set
1
1
0
M12L16161A
Operation temperature condition -40℃~85℃
JEDEC Standard Test Set (refresh counter test)
6
5
LTMODE
6
5
0
Burst Read and Single Write (for Write
Through Cache)
v =Valid
x =Don’t care
Bit2-0
000
001
010
011
100
101
110
111
0
1
Bits6-4
000
001
010
011
100
101
110
111
WT=0
1
2
4
8
R
R
R
Full page
Sequential
Interleave
WT=1
1
2
4
8
R
R
R
R
Burst length
Wrap type
Latency mode
Mode Register Write Timing
CAS Latency
R
R
2
3
R
R
R
R
Remark R : Reserved
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
Mode Register W rite
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.1
8/29
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
