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M12L2561616A-7TG2K 参数 Datasheet PDF下载

M12L2561616A-7TG2K图片预览
型号: M12L2561616A-7TG2K
PDF下载: 下载PDF文件 查看货源
内容描述: JEDEC标准的3.3V电源 [JEDEC standard 3.3V power supply]
分类和应用:
文件页数/大小: 45 页 / 933 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
SDRAM
M12L2561616A (2K)
4M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of
the system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
64ms refresh period (8K cycle)
ORDERING INFORMATION
Product ID
M12L2561616A-5TG2K
M12L2561616A-5BG2K
M12L2561616A-6TG2K
M12L2561616A-6BG2K
M12L2561616A-7TG2K
M12L2561616A-7BG2K
Max Freq.
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
Package
TSOP II
BGA
TSOP II
BGA
TSOP II
BGA
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN CONFIGURATION (TOP VIEW)
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S SQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
S SQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
2
3
4
5
6
7
8
9
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
A12
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
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