ESMT
SDRAM
M12L64164A
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6
μ
s refresh interval
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO.
M12L64164A-5TG
M12L64164A-6TG
M12L64164A-7TG
M12L64164A-5BG
M12L64164A-6BG
M12L64164A-7BG
MAX FREQ. PACKAGE Comments
200MHz
166MHz
143MHz
200MHz
166MHz
143MHz
54 TSOP II
54 TSOP II
54 TSOP II
54 VBGA
54 VBGA
54 VBGA
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
ORDERING INFORMATION
GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
Top View
V
DD
DQ 0
V
D D Q
DQ 1
DQ 2
V
S SQ
DQ 3
DQ 4
V
D D Q
DQ 5
DQ 6
V
S SQ
DQ 7
V
DD
LDQ M
WE
C AS
R AS
CS
A
13
A
12
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S SQ
DQ14
DQ13
V
D D Q
DQ12
DQ11
V
S SQ
DQ10
DQ 9
V
D D Q
DQ 8
V
SS
NC
UDQM
CLK
C KE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
54 Ball FVBGA (8mmx8mm)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 3.0
1/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
