ESMT
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register set
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
H
Auto Precharge Enable
Auto Precharge Disable
H
Auto Precharge Enable
H
H
All Banks
H
Clock Suspend or
Active Power Down
Entry
Exit
Entry
Precharge Power Down Mode
Exit
DQM
No Operating Command
L
H
H
H
X
L
H
H
H
H
L
V
X
X
X
X
X
V
V
V
H
L
H
L
L
H
L
L
H
H
X
H
X
H
X
X
X
H
V
X
X
V
X
X
V
X
X
X
X
X
X
X
X
X
X
L
L
H
L
H
H
L
L
X
X
L
H
L
L
X
X
L
H
L
H
X
H
CKEn-1
H
CKEn
X
H
L
H
X
L
L
L
H
H
L
L
H
X
L
L
H
X
H
H
H
X
H
X
X
X
X
CS RAS CAS
L
L
L
WE
M12S64322A
DQM BA0,1 A10/AP
X
OP CODE
X
A9~A0
Note
1,2
3
3
3
L
X
V
V
H
L
V
H
X
V
L
X
X
H
Row Address
L
Column
Address
(A0~A7)
Column
Address
(A0~A7)
3
4
4,5
4
4,5
6
Burst Stop
Bank Selection
Precharge
X
X
X
X
X
7
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note :
1.OP Code : Operating Code
A0~A10 & BA0~BA1 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4.BA0~BA1 : Bank select addresses.
If both BA1 and BA0 are “Low” at read ,write , row active and precharge ,bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read ,write , row active and precharge ,bank B is selected.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0
9/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
