ESMT
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register set
Auto Refresh
Entry
Self
Refresh
Exit
CKEn-1
H
H
L
H
H
CKEn
X
H
L
H
X
X
CS RAS CAS
L
L
L
H
L
L
L
L
H
X
L
H
L
L
H
X
H
L
WE
M12S64164A
A11,
BA0,
A10/AP
A9~A0
BA1
OP CODE
X
X
V
V
Row Address
Column
L
Address
H
(A0~A7)
Column
L
Address
H
(A0~A7)
X
L
H
X
DQM
X
X
X
X
X
X
Note
1,2
3
3
3
3
4
4,5
4
4,5
6
L
H
H
X
H
H
Refresh
Bank Active & Row Addr.
Auto Precharge Disable
Read &
Column Address Auto Precharge Enable
Auto Precharge Disable
Write &
Column Address Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
H
H
H
X
X
X
L
L
L
H
H
H
L
X
V
X
X
H
X
V
X
X
H
L
H
H
X
V
X
X
H
X
V
X
H
L
L
L
X
X
X
X
V
V
X
Clock Suspend or
Active Power Down
Entry
Exit
Entry
H
L
H
L
L
H
L
L
H
H
X
X
H
V
X
X
X
X
X
X
X
Precharge Power Down Mode
Exit
DQM
No Operating Command
L
H
H
X
H
X
L
H
L
V
V
X
H
X
X
X
7
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)
Note:
1.OP Code : Operating Code
A0~A11 & BA0 ~ BA1: Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4. BA0 ~ BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
7/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
