ESMT
SDRAM
M12S64322A
512K x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 2.5V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6μs refresh interval
ORDERING INFORMATION
Product No.
M12S64322A-6TG
M12S64322A-7TG
M12S64322A-6BG
M12S64322A-7BG
MAX FREQ. PACKAGE COMMENTS
166MHz
143MHz
166MHz
143MHz
TSOPII
TSOPII
90BGA
90BGA
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12S64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN ARRANGEMENT
Top View
V
DD
DQ0
V
DD Q
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DD Q
DQ5
DQ6
V
S S Q
DQ7
NC
V
DD
DQ M 0
WE
CA S
RA S
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
D QM 2
V
DD
NC
DQ 16
V
SS Q
DQ 17
DQ 18
V
DD Q
DQ 19
DQ 20
V
SS Q
DQ 21
DQ 22
V
DD Q
DQ 23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
S S
DQ1 5
V
SSQ
DQ1 4
DQ1 3
V
DD Q
DQ1 2
DQ1 1
V
SSQ
DQ 10
DQ9
V
DD Q
DQ8
NC
V
S S
DQ M 1
NC
NC
CL K
CK E
A9
A8
A7
A6
A5
A4
A3
DQ M 3
V
S S
NC
DQ3 1
V
DD Q
DQ3 0
DQ2 9
V
SSQ
DQ2 8
DQ2 7
V
DD Q
DQ2 6
DQ2 5
V
SSQ
DQ2 4
V
S S
8 6 Pin TSOP ( II )
(400mil x 875mil)
( 0 .5 m m P in pit ch )
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.1
1/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
