ESMT
Revision History
Revision 0.1 (15 Jan. 2002)
-
Original
Revision 0.2 (19 Nov. 2002)
-changed ordering information & DC/AC characteristics
Revision 0.1
M13S128168A - 5T
M13S128168A - 6T
Revision 0.2
M13S128168A - 6T
M13S128168A - 7.5AB
M13S128168A
Revision 0.3 (8 Aug. 2003)
-Change IDD6 from 3mA to 5mA.
Revision 0.4 (27 Aug. 2003)
-Change ordering information & DC / AC characteristics.
Revision 1.0 (21 Oct. 2003)
-Modify tWTR from 2tck to 1tck.
Revision 1.1 (10 Nov. 2003)
-Correct some refresh interval that is not revised.
-Correct some CAS Lantency that is not revised.
Revision 1.2 (12 Jan. 2004)
-Correct IDD1; IDD4R and IDD4W test condition.
-Correct tRCD; tRP unit
-Add tCCD spec.
-Add tDAL spec.
Revision 1.3 (12 Mar. 2004)
-Add Cas Latency=2; 2.5
Revision 1.4 (23 Jun. 2005)
-Add Pb-free to ordering information
-Modify IDD0 and IDD1 spec
-Modify some AC timing unit from tCK to ns.
Revision 1.5 (29 May. 2006)
-Delete CL2 ; CL2.5
-Modify tREFI
-Delete Non-pb-free form ordering information
Revision 1.6 (3 Jan. 2007)
-Add CL2.5
Revision 1.7 (12 Apr. 2007)
-Add BGA package
Revision 1.8 (01 Jun. 2007)
-Delete CL 2.5
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
1/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
