ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.375V ~ 2.75V, V
DDQ
= 2.375V ~ 2.75V
V
DD
= 2.6V ~ 2.8V, V
DDQ
= 2.6V ~ 2.8V [for speed -4]
Auto & Self refresh
15.6us refresh interval (64ms refresh period, 4K cycle)
SSTL-2 I/O interface
66 pin TSOPII and 60 ball BGA package
M13S128168A
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Ordering Information
PRODUCT NO.
M13S128168A -4TG
M13S128168A -5TG
M13S128168A -6TG
M13S128168A -4BG
M13S128168A -5BG
M13S128168A -6BG
MAX FREQ
250MHz
200MHz
166MHz
250MHz
200MHz
166MHz
2.7V
BGA
2.5V
VDD
2.7V
TSOPII
2.5V
PACKAGE
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 2.2
1/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
