ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3;4
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.375V ~ 2.625V, V
DDQ
= 2.375V ~ 2.625V
V
DD
= 2.5V ~ 2.7V, V
DDQ
= 2.5V ~ 2.7V [for speed -3.6]
Auto & Self refresh
32ms refresh period (4K cycle)
SSTL-2 I/O interface
144Ball FBGA and 100 pin LQFP package
M13S128324A
1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Ordering Information:
PRODUCT NO.
M13S128324A -3.6BG
M13S128324A -4BG
M13S128324A -5BG
M13S128324A -6BG
M13S128324A -4LG
M13S128324A -5LG
M13S128324A -6LG
MAX FREQ
275MHz
250MHz
200MHz
166MHz
250MHz
200MHz
166MHz
VDD
2.6V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
PACKAGE
144 Ball FBGA
144 Ball FBGA
144 Ball FBGA
144 Ball FBGA
100 pin LQFP
100 pin LQFP
100 pin LQFP
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 2.3
1/50
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
