ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.3V ~ 2.7V, V
DDQ
= 2.3V ~ 2.7V
V
DD
= 2.4V ~ 2.8V, V
DDQ
= 2.4V ~ 2.8V (for speed -4)
Auto & Self refresh
7.8us refresh interval
SSTL-2 I/O interface
66pin TSOPII and 60 Ball BGA package
M13S2561616A
4M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Ordering Information:
PRODUCT NO.
M13S2561616A -4TG
M13S2561616A -5TG
M13S2561616A -6TG
M13S2561616A -4BG
M13S2561616A -5BG
M13S2561616A -6BG
MAX FREQ
250MHz
200MHz
2.5V
166MHz
250MHz
200MHz
2.5V
166MHz
2.6V
BGA
Pb-free
VDD
2.6V
TSOPII
PACKAGE
COMMENTS
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2009
Revision : 2.0
1/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
