ESMT
M13S32321A
Essential Functionality for DDR SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from
the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM
until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
NOP
R EAD A
N OP
NO P
N OP
N OP
NO P
CO M M AND
NO P
N OP
D QS
C AS L a t en c y =3
D o u t0 Do u t 1 D o u t2
DQ' s
D o u t3
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1 16/50
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
